Wish Branch: A New Control Flow Instruction Combining Conditional Branching and Predicated Execution

As processor pipelines get deeper and wider and instruction windows get larger, the branch misprediction penalty increases. Predication has been used to reduce the number of branch mispredictions by eliminating hard-to-predict branches. However, with predication, the processor is guaranteed to fetch and possibly execute useless instructions, which sometimes offsets the performance advantage of having fewer mispredictions. Also, predication does not eliminate the misprediction penalty due to backward loop branches. This paper introduces a new type of branch called a wish branch. Wish branches combine the strengths of traditional conditional branches and predication, allowing instructions to be skipped over as with traditional branches, but also avoiding pipeline flushes due to mispredictions as with predication. Unlike traditional conditional branches, on a wish branch misprediction, the pipeline does not (always) need to be flushed. And, unlike predication, a wish branch (sometimes) avoids fetching from both paths of the control flow. This paper also describes a type of wish branch instruction, called a wish loop, which reduces the branch misprediction penalty for backward loop branches. We describe the software and hardware support required to generate and utilize wish branches. We demonstrate that wish branches can decrease the execution times of SPEC2000 integer benchmarks by 7.8% (up to 21%) compared to traditional conditional branches and by 3% (up to 11%) compared to predicated execution. We also describe several simple hardware optimizations for exploiting and increasing the benefits of wish branches.